Leveraging Stochastic Memristor Devices in Neuromorphic Hardware Systems

As the fourth basic circuit element, memristor has a unique synapse-Alike feature which demonstrates great potentials in neuromorphic circuit design. However, a large gap exists between the theoretical memristor characteristics and the actual device behavior. For example, though the continuous changing in resistance state is expected in neuromorphic circuit design, it is difficult to maintain arbitrary intermediate state. In addition, the stochastic switching behaviors have been widely observed in nano-scale memristor devices. In this work, we first developed a stochastic behavior model in order to facilitate the investigation on memristor-based hardware implementation. Our modeling was based on the statistical analysis of experimental data of {\rm TiO }2 device. By leveraging the stochastic behavior of memristors, a random number generator was proposed. We also presented a macro cell design composed of multiple parallel connecting memristors which can be successfully used in implementing the weight storage unit and the stochastic neuron. The designs of these fundamental components provide a feasible solution in memristor-based hardware implementation of neural networks.