Exploration of GPGPU register file architecture using domain-wall-shift- write based racetrack memory

SRAM based register le (RF) is one of the major factors lim-iting the scaling of GPGPU. In this work, we propose to use the emerging nonvolatile domain-wall-shift-write based race-track memory (DWSW-RM) to implement a power-effcient GPGPU RF, of which the power consumption is substantially reduced. A holistic technology set is developed to minimize the high access cost of DWSW-RWcaused by the sequential access mechanism. Experiment results show that our proposed tech-niques can improve the GPGPU performance by 4.6% com-pared to the baseline with SRAM based RF. The RF energy effciency is also signcantly improved by 2.45×. Copyright 2014 ACM.