A dual-mode architecture for fast-switching STT-RAM

TitleA dual-mode architecture for fast-switching STT-RAM
Publication TypeConference Paper
Year of Publication2012
AuthorsZ Sun, H Li, and W Wu
Conference NameProceedings of the International Symposium on Low Power Electronics and Design
Date Published09/2012

In the past, the spin-transfer torque RAM (STT-RAM) suffered from the slow write speed and the high write energy consumption. The latest progress in device engineering has dramatically reduced the write time to a few nanoseconds and hence enabled the fast-switching STT-RAM (FS-STT-RAM). However, the enhancement in write performance results in the degradation of read operations, in terms of both speed and data reliability. Our analysis shows that the read performance becomes critical. Based upon the tradeoff among the read latency, read errors, and system performance, we propose a new FS-STT-RAM architecture, which can switch between two operation modes for either high data accuracy or low power consumption with the support of operation system. In the high accuracy mode, FS-STT-RAM applies the rewrite-after-read scheme to eliminate the data disturbances induced by read current. Even so, with enhancement from shadow rewrite buffer and bit invert scheme, it gains an average 19% improvement in energy-delay-product (EDP) compared to a conventional STT-RAM. When an application can afford a very low chance of read disturbance, the proposed FS-STT-RAM can operate in the low power mode and further boost the average EDP improvement to 34%. © 2012 ACM.