Design exploration of racetrack lower-level caches

TitleDesign exploration of racetrack lower-level caches
Publication TypeConference Paper
Year of Publication2014
AuthorsZ Sun, X Bi, AK Jones, and H Li
Conference NameProceedings of the International Symposium on Low Power Electronics and Design
Date Published01/2014

The recent successful integration of magnetic racetrack memory forecasts a new computing era with unprecedentedly high-density on-chip storage. However, racetrack memory accesses require frequent magnetic domain shifting, introducing overheads in access latency and energy consumption. In this paper, we evaluate and compare several different physical layout strategies and array organizations. From this evaluation, a workload-oriented racetrack LLC architecture is proposed that combines different array types, each of which is tailored to a specific data access pattern. Further, a resizable cache access strategy is applied to reduce shifting overheads at runtime. Our simulation results show that compared with the leading racetrack-based cache, the proposed racetrack LLC can improve system performance by 13.2% reduce LLC energy consumption by 30.4%. Copyright 2014 ACM.