|Title||DEEP: Developing extremely efficient runtime on-chip power meters|
|Publication Type||Conference Paper|
|Year of Publication||2022|
|Authors||Z Xie, S Li, M Ma, CC Chang, J Pan, Y Chen, and J Hu|
|Conference Name||Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad|
Accurate and efficient on-chip power modeling is crucial to runtime power, energy, and voltage management. Such power monitoring can be achieved by designing and integrating on-chip power meters (OPMs) into the target design. In this work, we propose a new method named DEEP to automatically develop extremely efficient OPM solutions for a given design. DEEP selects OPM inputs from all individual bits in RTL signals. Such bit-level selection provides an unprecedentedly large number of input candidates and supports lower hardware cost, compared with signal-level selection in prior works. In addition, DEEP proposes a powerful two-step OPM input selection method, and it supports reporting both total power and the power of major design components. Experiments on a commercial microprocessor demonstrate that DEEP s OPM solution achieves correlation R > 0.97 in per-cycle power prediction with an unprecedented low area overhead on hardware, i.e., < 0.1% of the microprocessor layout. This reduces the OPM hardware cost by 4 - 6× compared with the state-of-the-art solution.