|Title||DA-RAID-5: A disturb aware data protection technique for NAND flash storage systems|
|Publication Type||Conference Paper|
|Year of Publication||2013|
|Authors||J Guo, W Wen, YZ Li, S Li, H Li, and Y Chen|
|Conference Name||Proceedings Design, Automation and Test in Europe, Date|
Program disturb, read disturb and retention time limit are three major reasons accounting for the bit errors in NAND flash memory. The adoption of multi-level cell (MLC) technology and technology scaling further aggravates this reliability issue by narrowing threshold voltage noise margins and introducing larger device variations. Besides implementing error correction code (ECC) in NAND flash modules, RAID-S are often deployed at system level to protect the data integrity of NAND flash storage systems (NFSS), however, with significant performance degradation. In this work, we propose a technique called "DA-RAID-S" to improve the performance of the enterprise NFSS under RAID-S protection without harming its reliability (here DA stands for "disturb aware"). Three schemes, namely, unbound-disturb limiting (UDL), PE-aware RAID-S and Hybrid Caching(HC) are proposed to protect the NFSS at the different stages of its lifetime. The experimental results show that compared to the best prior work, DA-RAID-S can improve the NFSS response time by 9.7% on average. © 2013 EDAA.