Combating write penalties using software dispatch for on-chip MRAM integration

Recent advances in the emerging memory technology magnetic RAM (MRAM) enrich the opportunities to build high density and low power embedded systems. One common way of utilizing MRAM is integrating it with conventional memories and distributing data to the appropriate type of memory to mitigate the high write penalty of MRAM. In this paper, we propose a software-based approach to identify data access characteristics and guide hardware to perform efficient data distribution. We use our technique to build an on-chip MRAM-SRAM hybrid cache and demonstrate an 86.8% reduction in leakage power, a 9.8% reduction in total power, and a 5% memory performance improvement, compared to a traditional static RAM (SRAM)-only cache. © 2009-2012 IEEE.