| Title | A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores |
| Publication Type | Conference Paper |
| Year of Publication | 2014 |
| Authors | J Wang, Y Tim, WF Wong, ZL Ong, Z Sun, and HH Li |
| Conference Name | Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac |
| Date Published | 03/2014 |
| Abstract | STT-RAM is an emerging NVRAM technology that promises high density, low energy and a comparable access speed to conventional SRAM. This paper proposes a hybrid L1 cache architecture that incorporates both SRAM and STT-RAM. The key novelty of the proposal is the exploition of the MESI cache coherence protocol to perform dynamic block reallocation between different cache partitions. Compared to the pure SRAM-based design, our hybrid scheme achieves 38% of energy saving with a mere 0.8% IPC degradation while extending the lifespan of STT-RAM partition at the same time. © 2014 IEEE. |
| DOI | 10.1109/ASPDAC.2014.6742958 |
