Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units

TitleCheckpoint-aware instruction scheduling for nonvolatile processor with multiple functional units
Publication TypeConference Paper
Year of Publication2015
AuthorsM Xie, C Pan, J Hu, C Yang, and Y Chen
Conference Name20th Asia and South Pacific Design Automation Conference, Asp Dac 2015
Date Published03/2015
Abstract

Embedded systems powered with harvested energy experience frequent execution interruption due to unstable energy source. Nonvolatile (NV) register based processor is proposed to realize fast resume after power failure. The states in the volatile registers are checkpointed to NV registers. However, frequent checkpointing causes performance degradation and consumes excessive power. In this paper, we propose the checkpoint aware instruction scheduling (CAIS) algorithm to reduce the writes to NV registers. Experiments show that CAIS can improve performance and reduce power consumption.

DOI10.1109/ASPDAC.2015.7059024