Cache coherence enabled adaptive refresh for volatile STT-RAM

TitleCache coherence enabled adaptive refresh for volatile STT-RAM
Publication TypeConference Paper
Year of Publication2013
AuthorsJ Li, L Shi, Q Li, CJ Xue, Y Chen, and Y Xu
Conference NameProceedings Design, Automation and Test in Europe, Date
Date Published01/2013

Spin-Transfer Torque RAM (STT-RAM) is extensively studied in recent years. Recent work proposed to improve the write performance of STT-RAM through relaxing the retention time of STT-RAM cell, magnetic tunnel junction (MTJ). Unfortunately, frequent refresh operations of volatile STT-RAM could dissipate significantly extra energy. In addition, refresh operations can severely conflict with normal read/write operations and results in degraded cache performance. This paper proposes Cache Coherence Enabled Adaptive Refresh (CCear) to minimize refresh operations for volatile STT-RAM. Through novel modifications to cache coherence protocol, CCear can effectively minimize the number of refresh operations on volatile STT-RAM. Full-system simulation results show that CCear approaches the performance of the ideal refresh policy with negligible overhead. © 2013 EDAA.