Accelerating graph computation with racetrack memory and pointer-assisted graph representation

TitleAccelerating graph computation with racetrack memory and pointer-assisted graph representation
Publication TypeConference Paper
Year of Publication2014
AuthorsE Park, S Yoo, S Lee, and H Li
Conference NameProceedings Design, Automation and Test in Europe, Date
Date Published01/2014
Abstract

The poor performance of NAND Flash memory, such as long access latency and large granularity access, is the major bottleneck of graph processing. This paper proposes an intelligent storage for graph processing which is based on fast and low cost racetrack memory and a pointer-assisted graph representation. Our experiments show that the proposed intelligent storage based on racetrack memory reduces total processing time of three representative graph computations by 40.2%∼86.9% compared to the graph processing, GraphChi, which exploits sequential accesses based on normal NAND Flash memory-based SSD. Faster execution also reduces energy consumption by 39.6%∼90.0%. The in-storage processing capability gives additional 10.5%∼16.4% performance improvements and 12.0%∼14.4% reduction of energy consumption. © 2014 EDAA.

DOI10.7873/DATE2014.172